Left: Example of a circuit pattern with 65 nm MFS. Right: An example for 32 nm MFS. Both patterns were generated using 193 nm radiation but the 32 nm example employed immersion, double patterning, and minimum dimensions only in the vertical direction. [Figures courtesy of Mark Bohr (ISSCC, Feb. 2009) and Yan Borodovsky, Intel Corporation.]
(Color online) Example of pitch division at 193 nm showing half-pitch. (Figures courtesy Yan Borodovsky, Intel Corporation.)
(Color online) Patterns featuring critical dimensions (CDs) generated by extreme ultraviolet lithography. Top: results of measured CDs generated without (left) and with (right) optical proximity correction. These CD statistical results were taken over 1010 measurement locations (every 5 nm) and show improved mean-to-target CD distributions for the corrected patterns. Below: SEM pictures of representative patterns (32 nm nominal linewidth). (Figures courtesy of ASML Co.)
(Color online) Evolution of variable-shaped beam mask writer resolution: 38 nm half-pitch NAND flash gate layer, 2008, left; 28 nm half-pitch contacts, 2009, center; and 22 nm half-pitch, 2010. (Photographs courtesy of DNP and MII.)
(Color online) Electron beam lithography system featuring 2500 programmable 50 keV electron beams of 12.5 nm beam diameter. The programmable aperture array (APS) provides the means for generating an array of beamlets that can be individually turned on and off. The bottom pictures show preliminary examples of generated patterns. (Photographs and figures courtesy of IMS.)
(Color online) Illustration of shot noise. The central square corresponds to a minimum feature defined by a random distribution of dots with a mean density of dots five times that of the surroundings. Left: central square with 160 dots, right: with 1280 dots. The two square outlines correspond to the allowed area within which the edges must lie after the resist is developed. How far this corresponds to electron beam exposure is arguable but is optimistic at best. See Refs. 10 and 12 .
(Color online) Electron beam technology: resolution vs beam current. What has been experimentally achieved and published in a refereed journal (or equivalent). A SEM has a single pencil beam. The mask writer, and EL1 and EL2, each have a VSB and so expose several pixels simultaneously. MAPPER employs an array of individually modulated pencil or fixed shape beams. SCALPEL, PREVAIL, LEEPL, and ELIPS feature electron optical projection of the required pattern. (Figure courtesy of Kristen Boucher.)
(Color online) Principle of distributed-axis electron beam technology (Ref. 14 ). The individual beams are separated such that the charge in one beam does not affect its neighbors. In this example the beams are separated by 0.25 mm. Each photoelectron beam is emitted from the photocathode into a uniform magnetic field and an accelerating electric field. In this way each beam has its own electron optical axis and is repeatedly focused back onto this axis by the magnetic field.
(Color online) Example of a system, MAPPER, that employs distributed-axis electron optics. The key numbers for the 22 nm node are 13 000 beams and data channels, 25 nm spot size, 13 nA current, 3.5 Gbyte/s data rate, 3.5 kV accelerating voltage, nominal dose, and pixel size at nominal dose of 3.5 nm (see Ref. 15 ).
(Color online) Examples of patterns exposed with MAPPER. Courtesy of David Rio, CEA, and LETI (Ref. 16 ).
Examples of patterns generated by a form of nanoimprinting. The numbers labeled refer to the dimensions of the pattern features. The uniformity of the critical dimension (CDU) within a field is less than 1.5 nm and the roughness of the feature edges is less than 2.0 nm. (Figures courtesy of Molecular Imprints Inc.)
Alternative approach to lithography for continuing the benefits of Moore’s law is to find a way to stack active devices vertically without lowering interconnect density (“monolithic three-dimensional integrated circuitry”). The key is to put down device-quality single crystal semiconductor islands on deposited amorphous layers without overheating the underlying (previously made) circuitry. Here is shown an array of silicon islands directly attached to a surface using Al/Ge eutectic bonding. The maximum temperature was , thus avoiding damage to underlying devices and interconnects. [Courtesy of Filip Crnogorac (Ref. 23 ).]
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