Estimation of line width roughness (LWR) parameters is necessary for semiconductor process optimization, comparison of next-generation lithography processes as well as device performance simulation. According to previous studies [V. Constantoudis et al., J. Vac. Sci. Technol. B21, 1019 (2003); J. Vac. Sci. Technol. B22, 1974 (2004)], a complete description of LWR can be provided by three parameters: root-mean square roughness , correlation length , and roughness exponent . However, the primary challenge in the estimation of the aforementioned LWR parameters is the limited availability of data in the scanning electron micrograph (SEM)image. A typical SEMimage consists of 8–20 lines of 300–1500 nm length. It has been recognized that for a given line, in the presence of correlation between line widths at a given separation, the estimate of for a finite length of line can be significantly biased. Furthermore, for next-generation lithography (NGL) technologies such as double patterning, the number of lines available to estimate each lithography step is cut in half since alternate lines are produced from different processes. Thus, there is a need for an estimation procedure that performs robustly for arbitrarily shorter and fewer numbers of lines. Using a vectorized block or block of blocks bootstrap technique for dependent data and a weighted least-squares (WLS) fitting procedure, the authors fit a specific form of a variogram model. Block of blocks bootstrap is used to estimate the variance of a variogram, which in turn provides the WLS weights. Additionally, the bootstrap approach also allows us to estimate the error in the estimated LWR parameters, a vital requirement that has not been addressed by any of the previously reported procedures on this subject. The authors’ procedure works even in the presence of some unknown local critical dimension (CD) variation or if there is a systematic difference in CD (by design or otherwise) between the lines. The authors validate their procedure with simulated roughness profiles with deterministic LWR parameters. Lastly, as an application of their procedure, they evaluate actual profiles from a variety of different mainstream NGL processes such as litho-freeze-litho-etch double patterning lithography, self-aligned double patterning, and extreme ultraviolet, as well as alternatives such as directed self-assembly and nanoimprint lithography. It was shown that can be overestimated by over two times if local variation is not treated properly.
This work would not have been possible without the gracious support of the following people who provided the wafers used in this article: Thomas Wallow at Global Foundries for providing SEM images of various lithographic process; Paul Nealey, Chi-Chun Liu, and Adam Welander (University of Wisconsin at Madison) for providing DSA wafers; Lloyd Litt and Matt Malloy (SEMATECH) for providing NIL wafers and CD-SEM metrology; Chris Bencher (Applied Materials) for providing SADP wafers; Mark Slezak (JSR Micro) for providing DPL images; Obert Wood, Mark Raymond, and Todd Ryan (GLOBALFOUNDRIES) for providing the EUV wafers; and Anita Fumar-Pici (ASML), Catherine Volkman (GLOBAL-FOUNDRIES), Hiroyuki Mizuno (Toshiba, USA), and Takumichi Sutani (Hitachi) for SEM measurement and metrology assistance. The authors would also like to thank Patrick Naulleau (LBNL) and Tyrone Vincent (Colorado School of Mines) for helpful discussions. K.P. would also like to thank Vassilios Constantoudis (IMEL) for the invigorating discussions and SanDisk management for providing the opportunity to conduct this work. S.N.L.’s research is partially supported by NSF Grant No. DMS 0707139. Portions of this work were performed by the Research Alliance Teams at various IBM Research and Development Facilities. The work at UC Berkeley was supported by AMD, Applied Materials, ASML, Cadence, Canon, Ebara, Hitachi, IBM, Intel, KLA-Tencor, Magma, Marvel, Mentor Graphics, Novellus, Panoramic, SanDisk, Spansion, Synopsys, Tokyo Electron Limited, and Xilinx with donations from Photronics and Toppan, and matching support by the U.C. Discovery Program.
A. Motivation and background
B. Our work
II. LINE WIDTH ROUGHNESS MODEL
A. LWR parameters
B. Variogram model
III. ESTIMATION OF MODEL PARAMETERS
A. Estimation of and
B. Estimation of
IV. ROBUST ESTIMATION OF LWR PARAMETERS
B. Optimal block length
V. RESULTS AND DISCUSSION
A. Simulated data
B. SEMimage acquisition and postprocessing of data
C. Validation using simulated data
D. Next-generation lithography processes
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