1887
banner image
No data available.
Please log in to see this content.
You have no subscription access to this content.
No metrics data to plot.
The attempt to load metrics for this article has failed.
The attempt to plot a graph for these metrics has failed.
Effect of gate capping configurations and silicon-on-insulator thickness with external stresses on partially depleted metal-oxide-semiconductor field-effect transistors
Rent:
Rent this article for
USD
10.1116/1.3534008
/content/avs/journal/jvstb/29/1/10.1116/1.3534008
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/29/1/10.1116/1.3534008
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Experimental setup of applying external stress on CESL-induced tensile or compressive MOSFETs and a cross-section micrograph with 70-nm-thick CESL; strain is calculated by lift distance and the distance from clamping one end to the lifting screw .

Image of FIG. 2.
FIG. 2.

(Color online) Transconductance comparisons of (a) CESL-induced low tensile and compressive -MOSFETs and (b) CESL-induced low tensile and high tensile -MOSFETs with , 70, and 90 nm.

Image of FIG. 3.
FIG. 3.

(Color online) Transconductance degradation of CESL-induced low tensile -MOSFETs under stress time of up to 100 min; inset shows the relevant threshold voltage shift of the same devices.

Image of FIG. 4.
FIG. 4.

(Color online) Input-referred voltage noise spectrum for (a) CESL-induced low and high tensile -MOSFETs with and 90 nm and (b) CESL-induced low tensile and compressive -MOSFETs with and 90 nm.

Image of FIG. 5.
FIG. 5.

(Color online) Normalized drain current for CESL-induced low tensile (L.T.), high tensile (H.T.), and high compressive (Com.) with for (a) -MOSFETs and (b) -MOSFETs, and regression (piezoresistive) coefficients of longitudinal and transverse directions.

Image of FIG. 6.
FIG. 6.

(Color online) Normalized drain current for with CESL-induced low tensile (a) -MOSFETs and (b) -MOSFETs and regression (piezoresistive) coefficients of longitudinal and transverse directions.

Loading

Article metrics loading...

/content/avs/journal/jvstb/29/1/10.1116/1.3534008
2011-01-10
2014-04-19
Loading

Full text loading...

This is a required field
Please enter a valid email address
752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Effect of gate capping configurations and silicon-on-insulator thickness with external stresses on partially depleted metal-oxide-semiconductor field-effect transistors
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/29/1/10.1116/1.3534008
10.1116/1.3534008
SEARCH_EXPAND_ITEM