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Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique
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10.1116/1.3551527
/content/avs/journal/jvstb/29/2/10.1116/1.3551527
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/29/2/10.1116/1.3551527
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Major process steps for fabricating -MOSFETs with the DP method. (a) Formation of gate oxide and poly-Si on Si wafer with LOCOS isolation. (b) Generation of first PR pattern (G1), followed by the first poly-Si etching. (c) Generation of second PR pattern (G2) after removing the first PR. (d) Completion of the poly-Si gate after second poly-Si etching and subsequent PR removal. (e) Formation of S/D structure.

Image of FIG. 2.
FIG. 2.

(Color online) Layouts of the first (G1) and second (G2) gate patterns for defining the gate pattern on the active region. Gate length of the final gate is determined by the overlap region of the two gate patterns.

Image of FIG. 3.
FIG. 3.

Typical optical emissive signal recorded during the main etching stage of the second gate etching with the original mask design. No end point was detected.

Image of FIG. 4.
FIG. 4.

(Color online) Cross-sectional SEM view of a MOSFET showing an etch-induced recess at the right side of the gate. Top illustration is used to help visualize the structure. The recess was formed during the G2 etching stage due to the failure of EPD.

Image of FIG. 5.
FIG. 5.

Optical emissive signal recorded during the main etching stage of the (a) first and (b) second gate etchings with the modified mask design. Successful EPD is achieved in the two etch steps.

Image of FIG. 6.
FIG. 6.

In-line SEM views of gate patterns on active region etched with (a) original and (b) modified mask designs. The etch recess phenomenon can be resolved with the modified mask design.

Image of FIG. 7.
FIG. 7.

Measured poly-Si gate length is shown as a function of nominal gate length .

Image of FIG. 8.
FIG. 8.

(Color online) Cumulative plots of poly-Si gates patterned with DP method with nominal lengths of 80, 300, and 400 nm and with conventional single patterning with nominal length of 350 nm. Each curve represents the results measured from 35 test structures.

Image of FIG. 9.
FIG. 9.

(a) Transfer characteristics measured at and 1.5 V and (b) output characteristics of a control device with gate length of 100 nm and width of measured at and .

Image of FIG. 10.
FIG. 10.

Transfer characteristics of a control device with gate length of 80 nm and width of measured at and 1.5 V. As compared with the device characteristics shown in Fig. 9(a), a much higher subthreshold leakage is observed in the device.

Image of FIG. 11.
FIG. 11.

Cross-sectional SEM image of an 80 nm poly-Si gate formed on active region.

Image of FIG. 12.
FIG. 12.

(Color online) Output characteristics of control, S/D-halo, and S-halo -MOSFETs with measured at and .

Image of FIG. 13.
FIG. 13.

Transfer characteristics of (a) S/D-halo and (b) S-halo -MOSFETs with measured at and 1.5 V.

Image of FIG. 14.
FIG. 14.

Transfer characteristics of (a) 15 control and (b) 15 S/D-halo -MOSFETs with measured at .

Image of FIG. 15.
FIG. 15.

Transfer characteristics of 15 S-halo -MOSFETs with measured at for (a) forward mode and (b) reverse mode. Forward mode is measured with the source grounded and the drain is applied with 1.5 V, while reverse mode is with the role of S/D switched.

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/content/avs/journal/jvstb/29/2/10.1116/1.3551527
2011-01-31
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/29/2/10.1116/1.3551527
10.1116/1.3551527
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