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Phase change random access memory featuring silicide metal contact and high- interlayer for operation power reduction
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10.1116/1.3584823
/content/avs/journal/jvstb/29/3/10.1116/1.3584823
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/29/3/10.1116/1.3584823
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) Simulated temperature profile of reset process of phase change memory devices fabricated in this work: (a) without and (b) with interlayer. A top TiW electrode and a bottom NiSi electrode were used. A 0.65 V, 30 ns pulse was applied and the temperature profiles were taken at the end of the pulse. The peak temperature located in the phase change (PC) layer or , and is higher in a device with the interlayer.

Image of FIG. 2.
FIG. 2.

(Color online) (a) Temperature as a function of time for a 0.65 V pulse with pulse widths of 30 ns (solid line) and 80 ns (dotted line). This device has a interlayer between and NiSi bottom electrode. (b) Simulated peak temperature recorded at the end of the voltage pulse as a function of pulse width. The magnitude of the voltage pulse is 0.65 V. A longer pulse width leads to a higher peak temperature.

Image of FIG. 3.
FIG. 3.

(Color online) Schematics showing the cross-section of devices fabricated in this work: (a) Control PCRAM device without interlayer and (b) PCRAM device with a interlayer between the phase change (PC) material and the NiSi bottom electrode contact. The phase change material is with 3.5 at. % of nitrogen. (c) transmission electron microscopy (TEM) cross-section images of PCRAM device with a interlayer. The TEM images were captured after a reset/set cycling test.

Image of FIG. 4.
FIG. 4.

Resistance vs voltage characteristics of typical PCRAM devices for (a) programming pulse width of 30 ns during the reset process and (b) for programming pulse width of 400 ns during the set process. The resistances have been normalized to the reset resistances of each corresponding device.

Image of FIG. 5.
FIG. 5.

Dependence of average applied voltage on pulse widths for the reset process. Employing a interlayer enables the PCRAM device to be switched using a lower applied voltage.

Image of FIG. 6.
FIG. 6.

(Color online) Plot of (a) reset programming current and (b) set programming current as a function of pulse width. By employing a interlayer, lower programming reset currents can be achieved with only a slight increase in programming set current. The devices have a circular contact area with diameter.

Image of FIG. 7.
FIG. 7.

Normalized cell resistances in set (open symbols) and reset (solid symbols) states plotted against the number of set/reset cycles for PCRAM devices (a) without interlayer and (b) with interlayer on a NiSi bottom electrode.

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/content/avs/journal/jvstb/29/3/10.1116/1.3584823
2011-05-06
2014-04-24
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Phase change random access memory featuring silicide metal contact and high-κ interlayer for operation power reduction
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/29/3/10.1116/1.3584823
10.1116/1.3584823
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