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Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly
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10.1116/1.4767237
/content/avs/journal/jvstb/30/6/10.1116/1.4767237
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/30/6/10.1116/1.4767237
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

(Color online) DSA pattern generation through plasma removal of the PMMA phase followed by transfer into the underlying trilayer stack.

Image of FIG. 2.
FIG. 2.

Optimization of the etch process parameters enabled distortion free PMMA removal and high fidelity etching of the hard mask layer. Top down SEM images of the BCP after PMMA removal and after hard mask etch for a high power and a low power etch process. By applying a low power etch process, PS pattern quality is improved and line wiggling during hard mask etch is significantly reduced.

Image of FIG. 3.
FIG. 3.

Etch transfer of 29-nm-pitch DSA fingerprint pattern into two different trilayer stacks: (a) 10 nm SiOx hardmask on 30 nm amorphous carbon OPL and (b) 20 nm SiARC on 65 nm spin-on carbon.

Image of FIG. 4.
FIG. 4.

(a) Top down SEM images of the hardmask, OPL, and SiN etch. (b) Cross-sectional SEM images of SOI, TEOS SiO2, and SiN patterning.

Image of FIG. 5.
FIG. 5.

Example of 1, 2, and 11 self-assembled lines templated by graphoepitaxy, etch transferred into SiN. The number of templated lines is determined by the HSQ trench width.

Image of FIG. 6.
FIG. 6.

Top down SEM images of DSA patterning into SOI with two different hard mask materials, SiN, TEOS SiO2, and a SiN/Si/HKMG gate stack. Cross-sectional SEM image of the 40-nm-thick SiN pattern is also shown.

Image of FIG. 7.
FIG. 7.

(Color online) (a) Line and trench CD, (b) LER, and (c) LWR evolution of DSA patterned SiN during the SiOx hard mask, OPL, and final SiN etch processes.

Image of FIG. 8.
FIG. 8.

(Color online) LER and LWR evolution for DSA patterned 20 nm SOI lines with two different hard masks: (a) and (b) 10 nm SiOx and (c) and (d) 10 nm SiN, during the hard mask, OPL, and final SOI etch processes.

Image of FIG. 9.
FIG. 9.

(Color online) (a) LER and (b) LWR evolution of DSA patterned TEOS SiOx during the SiN hard mask, OPL, and final TEOS SiOx etch processes.

Image of FIG. 10.
FIG. 10.

(Color online) Final LER values for the DSA materials patterned materials shown in Fig. 5.

Image of FIG. 11.
FIG. 11.

Top down SEM images of DSA patterned SOI substrates before and after two different H2 conditions. (a) Before H2 anneal; LER = 2.8 nm, (b) after H2 annealing at 875 °C for 10 min; LER = 2.6 nm, (c) after H2 annealing at 900 °C for 10 min; LER = 1.4 nm.

Image of FIG. 12.
FIG. 12.

(Color online) PSD of LER and LWR for DSA patterned SOI lines before and after 900 °C H2 annealing.

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/content/avs/journal/jvstb/30/6/10.1116/1.4767237
2012-11-26
2014-04-16
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/30/6/10.1116/1.4767237
10.1116/1.4767237
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