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Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices
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Image of FIG. 1.
FIG. 1.

(Color online) Illustration of resist pattern aspect ratio (AR) limitations.

Image of FIG. 2.
FIG. 2.

(Color online) Examples of isolated (a)–(c) and dense (d)–(f) pattern designs. By adding larger patterns at their extremities, their stability is increased. Thus, (a) and (d) are the least stable configurations and (c) and (f) the most efficient ones.

Image of FIG. 3.
FIG. 3.

(Color online) Description of the capped amorphous carbon hard mask stack.

Image of FIG. 4.
FIG. 4.

(Color online) Description of the amorphous carbon hard mask process in its two configurations (without and with a-C trimming).

Image of FIG. 5.
FIG. 5.

(Color online) Scheme of a FDSOI transistor.

Image of FIG. 6.
FIG. 6.

(Color online) Scheme of FDSOI transistor gate stack combined with the a-C process stack.

Image of FIG. 7.
FIG. 7.

SEM cross sectional views of gate photoresist patterns performed through hybrid lithography process. Dimensions are 30 (a), 50 (b), and 70 nm (c).

Image of FIG. 8.
FIG. 8.

(Color online) Simulations performed with CASINO software in order to (i) compare back-scattering and forward-scattering effects simulated at acceleration voltages 100 kV (a) and 5 kV (b); and (ii) show the difference of energy deposition at 5 kV between 80 nm (c) and 30 nm (d) photoresist film thickness. Simulation materials: silicon substrate, PMMA resist.

Image of FIG. 9.
FIG. 9.

SEM cross sectional views of amorphous carbon (a-C) patterns achieved without (a) and with a-C trimming (b).

Image of FIG. 10.
FIG. 10.

SEM cross sectional views of FDSOI gates achieved with the capped a-C hard mask process. The graph represents the gate reduction evolution obtained by adjusting the a-C trimming step.

Image of FIG. 11.
FIG. 11.

(Color online) Graph representing the gate final dimension (nm) versus amorphous carbon trimming time (s). Initial resist pattern dimensions (isolated, dense 1:3) are 30, 50, and 70 nm.

Image of FIG. 12.
FIG. 12.

TEM cross sectional view of a 25 nm FDSOI transistor fabricated with the capped a-C hard mask trimming process (initial resist pattern dimensions: 50 nm).

Image of FIG. 13.
FIG. 13.

(Color online) Ioff = f(Ion) graphs for 25 nm FDSOI N-MOS (a) and P-MOS (b) transistors.


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Chemically amplified resist aspect ratio limits versus the nature of patterns.

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CD results obtained after hybrid lithography (e-beam/DUV) and gate stack etching.

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Negative photoresist pattern characterization (dimensions: 30, 50 and 70 nm).

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Etching chemistries used during amorphous carbon hard mask and gate stack patterning. (All etching steps were performed in the same etching chamber–DPS 2 from Applied Materials.)


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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices