Schematic representation of the bands for accumulation in an NMOS (p-type substrate) (left) and inversion in a PMOS (n-type substrate) (right). The recoverable charge defects are crudely represented by the distribution shown in the oxide. Note that tunneling of the holes (•) to the defect states is less likely in the NMOS accumulation case than in the PMOS inversion case.
Measured threshold voltage shift due to NBTI at 90 °C for a PMOS (Δ) and NMOS (O) stressed for 1500 s at Vgs = −3.50 and −3.75 V, respectively, followed by 1500 s of relaxation at Vgs = 0 V.
Measured threshold voltage shift at 90 °C for a PMOS (Δ) and NMOS (O) for oscillating positive (+1.5 V) and negative (−1.0 V) gate biasing following the 1500 s of stress and 1500 s of relaxation shown in Fig. 2 .
Measured IS component of the threshold voltage shift at 90 °C for a PMOS (Δ) and NMOS (O) as a function of accumulated stress time.
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