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Insight into the multicomponent nature of negative bias temperature instability
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10.1116/1.4796115
/content/avs/journal/jvstb/31/3/10.1116/1.4796115
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/31/3/10.1116/1.4796115
View: Figures

Figures

Image of FIG. 1.
FIG. 1.

Schematic representation of the bands for accumulation in an NMOS (p-type substrate) (left) and inversion in a PMOS (n-type substrate) (right). The recoverable charge defects are crudely represented by the distribution shown in the oxide. Note that tunneling of the holes (•) to the defect states is less likely in the NMOS accumulation case than in the PMOS inversion case.

Image of FIG. 2.
FIG. 2.

Measured threshold voltage shift due to NBTI at 90 °C for a PMOS (Δ) and NMOS (O) stressed for 1500 s at V = −3.50 and −3.75 V, respectively, followed by 1500 s of relaxation at V = 0 V.

Image of FIG. 3.
FIG. 3.

Measured threshold voltage shift at 90 °C for a PMOS (Δ) and NMOS (O) for oscillating positive (+1.5 V) and negative (−1.0 V) gate biasing following the 1500 s of stress and 1500 s of relaxation shown in Fig. 2 .

Image of FIG. 4.
FIG. 4.

Measured IS component of the threshold voltage shift at 90 °C for a PMOS (Δ) and NMOS (O) as a function of accumulated stress time.

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/content/avs/journal/jvstb/31/3/10.1116/1.4796115
2013-03-22
2014-04-20
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752b84549af89a08dbdd7fdb8b9568b5 journal.articlezxybnytfddd
Scitation: Insight into the multicomponent nature of negative bias temperature instability
http://aip.metastore.ingenta.com/content/avs/journal/jvstb/31/3/10.1116/1.4796115
10.1116/1.4796115
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