Volume 4, Issue 3, May 1986
Index of content:
Distortion correction and overlay accuracies achieved by the registration method using two‐stage standard mark system4(1986); http://dx.doi.org/10.1116/1.583595View Description Hide Description
A registration method using the two‐stage standard mark system is developed for high accuracy overlaying of patterns on a deformed wafer in an electron beam lithographic system used for direct wafer writing of 0.5 μm very large‐scale integrated (VLSI) patterns. Deflection distortions are corrected according to height z of a pattern writing field on a wafer. In this paper, deflection distortion correction and overlay accuracies are examined experimentally. Main field (2.6×2.6 mm) distortions are corrected using the third‐order power function of the main field coordinates (X, Y). Correction coefficients related to shift, deflection gain, and deflection rotation are shown to be a linear function of z, in spite of varying the beam focusing level with z. Each distortion expressed in terms up to the third‐order power of (X, Y) can be corrected with an accuracy within 0.02 μm. Overlay accuracies within 0.12 μm (3σ) are yielded when two‐layer test patterns are exposed on a wafer deformed about 75 μm in the Z direction.
Dependence of minimum linewidth on electron‐beam properties in submicron lithography using a rectangular beam4(1986); http://dx.doi.org/10.1116/1.583596View Description Hide Description
The relation between beam properties and minimum linewidth for a rectangular electron beam for submicron lithography is obtained through experiments and electron scattering simulation. Patterns are exposed in a 0.5‐μm‐thick PMMA resist film on a silicon wafer. The result gives a guiding principle in designing an electron‐optical column of a rectangular electron‐beam exposure system. A minimum linewidth of 0.5 μm can be obtained using a beam with a beam edge width δ=0. 18 μm at a beam voltage V a=25 kV and 0.2‐μm minimum linewidth using a beam with δ=0.08 μm at V a=30 kV.
4(1986); http://dx.doi.org/10.1116/1.583597View Description Hide Description
An electron beam pattern inspection system (EBIS) using digital image processing is presented. A pattern‐to‐data comparison method is used in this system to detect systematic, random and repeating defects of VLSI circuit patterns. The inspection data are generated from the design data, and transferred from a computer aided design (CAD) system via a computer network. In order to obtain the information of mask or wafer patterns, a low‐energy scanning electron microscope, which has the advantage of avoiding damage to the active devices and not charging the surface, is used. Frame memories are installed to store the inspection data and the actual pattern image. An extra image processor preprocesses the pattern image to obtain high signal‐to‐noise ratio and manipulates these images to extract defects. Two algorithms extracting the defects are studied. Spatial differentiation followed by a thresholding operation is a suitable procedure for the signal with drift.
4(1986); http://dx.doi.org/10.1116/1.583598View Description Hide Description
A monodisperse negative Si‐containing photoresist (MAS) has been developed for use as the top imaging layer for a bilayer system. MAS is a formulation of poly(allyldimethylsilyl‐α‐methylstyrene) (PMA Si) and a bisazide. PMA Si was synthesized by anionic polymerization of the monomer with n‐butyl lithium in THF at −78 °C. The polymer has a high softening point (T s =164–166 °C) and a narrow molecular weight distribution (M w=41 400, M w/M n=1.05). Near‐UV‐exposure has been carried out using a Kasper 2001 P contact printer. The D i g of MAS (0.2 μm in thickness) is 4.5 mJ/cm2 on a Si wafer and the γ value is over 2.0. The thickness reductions of MAS and MP‐1300 have been measured under various O2‐RIE conditions. The etching ratio of MP‐1300/MAS ranges from 3:1 to 10:1 depending on conditions and is decreased with an increase in rf power and with a decrease in chamber pressure. Under the optimized development and O2‐RIE condition, 0.75 μm line and space (L/S) patterns were accurately fabricated on the Si wafer having 0.5 μm high step. It is also noteworthy that 2.0 μm L/S patterns with a steep profile were obtained even in the MP‐1300 layer of 4.0 or 6.0 μm in thickness.
4(1986); http://dx.doi.org/10.1116/1.583599View Description Hide Description
Reactive ion stream etching has been developed for highly accurate etching with little bombardment induced damage by utilizing an electron cyclotron resonance (ECR) plasma. The ion energy during etching is controlled by utilizing the interaction between the ECR plasma and a divergent magnetic field, in a low energy range from 20 to 50 eV at low gas pressures of 10− 2 Pa. Highly accurate submicron patterns of polysilicon and molybdenum were obtained with high selectivities to SiO2, larger than 30, by using Cl2 gas as the main etching gas.
4(1986); http://dx.doi.org/10.1116/1.583600View Description Hide Description
We have investigated reactive ion beametching of semiconductor and insulator materials using gases, such as CF4 and C2F6, and compared the etching rates with those of argon ion milling. The ion beam is generated by a Kaufman‐type ion source, in a milling system manufactured by the Commonwealth Scientific Corporation. When a number of semiconductors such as InGaAs,InP,GaAs, Si, and Ge are etched with an argon ion beam, the etch rate of these materials increases linearly with the increase of beam current density. Quite different behavior is seen when CF4 or C2F6ion beams are used; the etch rate deviates from a linear dependence of current density at high beam current density. The etch rates of all the above materials using Ar are higher than the etch rates using CF4 or C2F6. However, for substrates of SiO2, BaO, LiNbO3, and both C2F6 and CF4 give better linearity and higher etching rates than argon. There is some evidence to suggest that at high beam currents, CF4 and C2F6 cause accumulation of carbon on the surface. Carbon buildup on the SiO2, BaO, LiNbO3, and other oxides is minimal since the oxygen in the lattice will form volatile products with carbon in the form of CO, CO2, or COF2, and therefore better linearity is seen. We report that the dependency of III–V compound etching rates on current density can be adjusted both by adjusting the axial magnetic field and introduction of oxygen. We also report the differential etching ratio between photoresist and semiconductor materials for gases C2F6, CF4, Ar/O2, and Ar. We show that the differential etching ratio is best for C2F6 gas.
4(1986); http://dx.doi.org/10.1116/1.583601View Description Hide Description
High rate masked etching of III–V materials such as GaAs and InP is needed for device processing requirements, such as via formation and chip separation. We have investigated the use of magnetron enhanced reactive ion etching to etchGaAs using photoresist as a mask. This technique gives unmasked etch rates up to 7 μm/min in GaAs. With an adequate heat sink, a photoresist mask shows little degradation for etch rates up to 1.2 μm/min with an undercut less than about 0.5 μm. Mechanisms of these results and directions for future work are presented.
4(1986); http://dx.doi.org/10.1116/1.583602View Description Hide Description
Hydrogen doping of Tafilms before thermal oxidation affects the dc leakage current in oxidizedTafilms. Metal‐insulator‐semiconductor (MIS) capacitors of Al/Ta2O5 (40 nm thick)/Si‐substrate structures have been prepared for the electrical measurements. The Tafilms were reactively sputtered on p‐type Si substrates in a mixture of Ar and H2 gases suitable for hydrogen doping. The hydrogen doping was found to be effective in reducing the leakage current in the Ta2O5films to be less than 10− 3 times that of undoped films, especially after low temperature oxidation at 400 °C. Secondary ion mass spectrometry(SIMS) analysis showed that the incorporation in the Ta2O5films of Si from the substrate was decreased by the presence of hydrogen during sputtering. A possible explanation for the reduction of leakage current caused by hydrogen doping is that the prevention of Si entry into Ta2O5films reduces the density of oxygen vacancies induced by unsaturated SiO x (x<2). This is thought to suppress the Poole–Frenkel‐type conduction in the Ta2O5films.
4(1986); http://dx.doi.org/10.1116/1.583603View Description Hide Description
A parallel beam reflection technique has been developed in our laboratory for measuring intrinsic residual stress for Si wafers thermally oxidized at temperatures of 600–1150 °C. A detailed description of this technique is provided, and stress values calculated for thermally grown SiO2 films on Si are consistent with those reported in the literature. Low temperature thermal oxidations resulted in compressive intrinsic SiO2 stresses greater than 4×109 dyn/cm2.
4(1986); http://dx.doi.org/10.1116/1.583563View Description Hide Description
Auger electron spectroscopy,Rutherford backscattering,secondary ion mass spectrometry, and transmission electron microscopy have been used to study the material properties of titanium silicide films prepared at 450 °C by plasma‐enhanced CVD on polysilicon, single crystal Si, and thermally grown SiO2 substrates. Three amorphous layers are deposited, the middle one containing Ti and Si, and the outer layers Si only. A 650 °C anneal is sufficient to form a 14 μΩ cm, large grain, stoichiometric TiSi2film of good purity. Oxidation of TiSi2/Si produces a Ti‐free SiO2 layer over the silicide. However, after prolonged oxidation, voids are found in the oxide layer and the silicide film becomes discontinuous. This can be prevented by oxidizing only the excess Si remaining after TiSi2 formation. During oxidation of the silicide deposited on SiO2 substrates, TiSi2 is decomposed into TiO x and SiO2.
4(1986); http://dx.doi.org/10.1116/1.583564View Description Hide Description
The pyrolytic decomposition of tetraethylorthosilicate (TEOS) has been used to deposit highly doped borophosphosilicate glass (BPSG) films. The experiments were carried out in a modified low pressurechemical vapor depositionfurnace in the 620–680 °C range at a deposition pressure of 0.5 Torr. Trimethylborate and phosphine together with oxygen were found to be the best dopant source combination. The deposited layers adhere strongly to the quartzware and low particle counts of typically less than 0.2 per cm2 were measured. The thickness uniformity was below ±6%, the dopant uniformity was ±0.1 wt. % over a wafer. If compared to low pressure SiH4–BPSG films, the TEOS–BPSG shows superior step coverage and much higher chemical stability up to dopant levels of about 5 wt. % B, 5 wt. % P. The etch rate behavior in buffered HF corresponds to the trends reported for SiH4–BPSG. The electrical characterization of thin TEOS–BPSG and TEOS–SiO2 layers yielded an electrical breakdown strength in the 7–8 MV/cm range. The glass flow properties (wet and dry ambient) were investigated and found to be very good in the 800–850 °C region. By using a rapid optical annealsystem, the required step tapering could be achieved at time/temperature combinations of 40 s/900 °C or 10 s/1000 °C. Detailed infrared studies showed strong interaction among the different oxide absorption bands of the TEOS–BPSG layers.
4(1986); http://dx.doi.org/10.1116/1.583559View Description Hide Description
Pt filmsdeposited by electron‐beam evaporation onto both heated and unheated Si substrates have been used to form PtSi by different annealing sequences and ambients. Pt filmsdeposited on substrates at 350 °C show complete formation of PtSi. Subsequent annealing at 550 °C is needed to form the protective oxide desired for device processing, with little dependence on the annealing ambients used. Pt filmsdeposited on unheated substrates, on the other hand, show a partial formation of Pt2Si. The formation of PtSi by further annealing of such films is clearly dependent on the annealing sequence and ambient used. A three‐temperature sequence at 200/300/550 °C in forming gas is shown to allow a complete reaction between Pt and Si, and to develop a surface protective oxide of excellent resistance against etching in aqua regia. PtSi films formed by single‐temperature annealing at 550 °C in various ambients, however, show incomplete reactions between Pt and Si, leaving unreacted Pt and traces of Pt2Si, and a surface passivating oxide of poor resistance against aqua regia. The results on such evaporated Pt films are therefore similar to those reported earlier for the sputtered Pt. Film structures and compositions, phases formed, and Schottky diodes using different processes are analyzed and compared with those using sputtered Pt.
4(1986); http://dx.doi.org/10.1116/1.583560View Description Hide Description
A technique for enhancing the conductivity of polysilicon interconnects by self‐aligned layers of platinum has been developed. A sheet resistance of approximately 1 Ω/⧠ was achieved for an interconnect height of 270 nm. Very thin layers of platinum have also been used to provide self‐alignment of other metals such as nickel,titanium, and aluminum.Nickel and titanium required prolonged ultrasonic processing to achieve self‐alignment to the polysilicon, as their specific stiffness coefficients were less favorable than that of platinum.Aluminum self‐alignment was only achieved after overlaying with films of nickel and platinum, and subsequently removing the latter layers by dissolving the nickel in fuming nitric acid. Polysilicon interconnects enhanced with a layer of self‐aligned aluminum yielded a sheet resistance of 1.2 Ω/⧠ for a total interconnect height of 120 nm. Metal‐oxide semiconductor(MOS) transistors and ring oscillators manufactured with metal enhanced interconnects showed no degradation effects when compared to those manufactured by the standard MOS process. Therefore, the process offers the advantages of self‐aligned source and drain regions and high yields associated with polysilicon gate technology together with those of a highly conducting metal gate.
Auger electron spectroscopy evaluation of voids in aluminum–1% silicon integrated circuit metallization4(1986); http://dx.doi.org/10.1116/1.583561View Description Hide Description
The internal surface of voids present in aluminum–1% siliconmetallization used in integrated circuits has been examined using Auger electron spectroscopy(AES). This surface was coated with a thin (<20 Å) layer of Al2O3 in addition to nitrogen, which is believed to represent the grain boundary structure prior to void formation. Both the metal fracture surface adjacent to the void and the void surface itself showed nonequilibrium silicon concentrations of 4–6 at. % and oxygen concentrations of 9–17 at. %. The oxygen on the metal fracture surface was not associated with Al2O3 or SiO2; rather, from residual gas analysis (RGA) of the sputtering environment, it is believed to be incorporated as the OH radical or water. High Si and O concentrations indicated the fracture site to be a grain boundary. Thus H, Si, O (or H2O), and N appear to be the contaminants associated with void formation and/or embrittlement in thin aluminum films.
The effects of germanium concentration on the compound formation and morphology of gold‐based contacts to gallium arsenide4(1986); http://dx.doi.org/10.1116/1.583565View Description Hide Description
Alloyed Au–Ge thin films on n‐GaAs are widely used for fabricating Ohmic contacts to n‐type GaAs. This paper presents a systematic study of the effects of Ge concentration on the compound formation and morphology in the metallization. The lowest annealing temperature at which the compound formation at 10− 6 Torr was observed for Au–Ge contacts with Ge concentrations of 0, ∼0.6, 3, and 12 wt. % Ge was 500, 500, 450, and 350 °C, respectively. Hence, Ge was found to decrease the compound formation temperature. Au7Ga2 was observed in contacts with low Ge concentrations (0 and ∼0.6 wt. % Ge), whereas α’‐AuGa (or Au7Ga), a tentatively identified Au3Ga phase, and a AuGeAs ternary phase were observed in contacts with a Ge concentration of 12 wt. %. At an intermediate Ge concentration (3 wt. % Ge), both Au7Ga2 and α’‐AuGa were observed. The morphology after compound formation was sensitive to the Ge concentration. In Au–Ge contacts, a change in the Ge concentration from 0 to ∼0.6 wt. % caused a sharp decrease in the aspect ratio of the aligned Au7Ga2 rectangular particles; a change from 3 to 12 wt. % Ge caused a change from a GaAs‐rich matrix to a Au‐rich matrix with the appearance of characteristically shaped AuGeAs patches.
Quantum‐well charge‐coupled devices for charge‐coupled device‐addressed multiple‐quantum‐well spatial light modulators4(1986); http://dx.doi.org/10.1116/1.583562View Description Hide Description
We have demonstrated a new type of GaAs/AlGaAs charge‐coupled device(CCD) in which the charge is confined to a quantum‐well channel. The MBE‐grown quantum‐well CCD (designated QWCCD) has a channel consisting of a 140 Å GaAs layer clad on both sides by AlGaAs layers. This structure was grown on a multiple‐quantum‐well (MQW) structure consisting of 60 periods of GaAs and AlGaAs layers of about 100 Å thickness each. Large optical modulationeffects involving quantum‐confined excitons were observed in the MQW structure when a bias was applied perpendicular to the plane of the layers. The combination of QWCCD and MQW structures has promise as a high‐speed spatial light modulator for applications in optical signal processing.