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Impact of Sn/Zn ratio on the gate bias and temperature-induced instability of Zn-In-Sn-O thin film transistors

Appl. Phys. Lett. 95, 173508 (2009); doi:10.1063/1.3257726

Published 29 October 2009

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Min Ki Ryu,1 Shinhyuk Yang,1 Sang-Hee Ko Park,1 Chi-Sun Hwang,1 and Jae Kyeong Jeong2
1Transparent Electronics Team, ETRI, Daejeon 305-700, Republic of Korea
2Department of Materials Science and Engineering, Inha University, 253 Yonghyun-Dong, Nam-Gu, Incheon 402-751, Republic of Korea
We investigated the effect of the Sn/Zn ratio in the amorphous Zn-In-Sn-O (ZITO) system on the gate voltage stress-induced stability of the resulting thin film transistors (TFTs). The device stability of the TFTs with a composition channel of Zn:In:Sn=0.35:0.20:0.45 (device C) was dramatically improved, while those of the devices with Zn:In:Sn=0.45:0.20:0.35 and 0.40:0.20:0.40 suffered from deep level trap creation in the channel and charge trapping, respectively. The stability enhancement of device C can be attributed to its having the lowest total trap density, which was corroborated by the superior temperature stability of the subthreshold current region in the temperature range from 298 to 398 K. Therefore, the Sn atoms are believed to act as a stabilizer of the amorphous ZITO network, which is similar to the role of Ga in the In-Ga-Zn-O system. ©2009 American Institute of Physics
History: Received 15 August 2009; accepted 10 October 2009; published 29 October 2009
Permalink: http://link.aip.org/link/?APPLAB/95/173508/1
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KEYWORDS and PACS

Keywords
PACS
  • 85.30.Tv
    Semiconductor field effect devices
  • 71.55.Ht
    Impurity and defect levels in other nonmetals
  • YEAR: 2009

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0003-6951 (print)   1077-3118 (online)
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