Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates
Appl. Phys. Lett. 95, 183504 (2009); doi:10.1063/1.3256223
Published 4 November 2009
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This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ~680 cm2/V s, on/off ratios >107, gate leakage current densities <2.8×10−7 A/cm2, and subthreshold slopes ~120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.
©2009 American Institute of Physics
| History: | Received 20 August 2009; accepted 4 September 2009; published 4 November 2009 |
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http://link.aip.org/link/?APPLAB/95/183504/1 |
KEYWORDS and PACS
PUBLICATION DATA
0003-6951 (print)
1077-3118 (online)
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