P-6: A Novel Self-Aligned Lightly-Doped-Drain Polysilicon Thin-Film Transistor Using a Partial Exposure Technique
In this paper, a novel self-aligned lightly-doped-drain (LDD) Poly-Si TFT using a partial exposure technique is proposed and demonstrated. The LDD region is self-aligned to the channel and with a leng...
P-8: Reliability of Single-Crystalline Si TFTs Fabricated inside a Location-Controlled Grain
The reliability of TFTs (W/L= 2.03/1.87 µm) fabricated inside a grain formed by µ-Czochralski process was studied under static bias stress. Upon drain stress up to 14V with 300 sec, there ...
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