Exploiting temporal loads for low latency and high bandwidth memory
Increasing clock frequencies and issue rates aggravates the memory latency problem, imposing higher memory bandwidth requirements. While caches can be multi-ported to provide high memory bandwidth, th...
Increasing clock frequencies and issue rates aggravates the memory latency problem, imposing higher memory bandwidth requirements. While caches can be multi-ported to provide high memory bandwidth, th...
Focalising dynamic value prediction to CPU's context
Value prediction (VP) is a relatively new technique that increases performance by eliminating true data dependency constraints. VP architectures allow data dependent instructions to issue and execute ...
Value prediction (VP) is a relatively new technique that increases performance by eliminating true data dependency constraints. VP architectures allow data dependent instructions to issue and execute ...
Topology adaptive network-on-chip design and implementation
IEE Proc., Comput. Digit. Tech. -- July 2005 -- Volume 152, Issue 4, p.467–472
doi:10.1049/ip-cdt:20045016
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Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput.
| History: | Received 29 April 2004; revised 13 July 2004 |
| Permalink: | http://dx.doi.org/10.1049/ip-cdt:20045016 |
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