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Balanced ternary addition using a gated silicon nanowire

Source: Appl. Phys. Lett. 99, 263109 (2012); http://dx.doi.org/10.1063/1.3669536

Published 29 December 2011

KEYWORDS and PACS
Keywords
PACS
  • 84.30.Sk
    Pulse and digital circuits
  • 85.35.Gv
    Single electron devices
  • YEAR: 2011
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PUBLICATION DATA
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J. A. Mol,1,2 J. van der Heijden,2 J. Verduijn,1,2 M. Klein,3 F. Remacle,4 and S. Rogge1,2
1Centre for Quantum Computation & Communication Technology, School of Physics, University of New South Wales, Sydney, New South Wales 2052, Australia
2Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, 2628 CJ Delft, The Netherlands
3The Fritz Haber Research Center for Molecular Dynamics, The Hebrew University of Jerusalem, Jerusalem 91904, Israel
4Département de Chimie, B6c, Université de Liège, B4000 Liège, Belgium
Ternary logic has the lowest cost of complexity, here, we demonstrate a CMOS hardware implementation of a ternary adder using a silicon metal-on-insulator single electron transistor. Gate dependent rectifying behavior of a single electron transistor (SET) results in a robust three-valued output as a function of the potential of the single electron transistor island. Mapping logical, ternary inputs to the three gates controlling the potential of the single electron transistor island allows us to perform complex, inherently ternary operations, on a single transistor. ©2011 American Institute of Physics
History: Received 11 October 2011; accepted 23 November 2011; published 29 December 2011
Digital Object Identifier: http://dx.doi.org/10.1063/1.3669536

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