Resonant tunneling (RT) of electrons through a double-barrier (DB) structure¹ has been studied because of the physical and technological interests. The negative differential resistance (NDR) due to RT has been reported for heteroepitaxial systems, such as GaAs/AlGaAs^1,2 and Si/SiGe,³ and recently for a single-crystalline-Si/amorphous-SiO₂ system by the authors.^4,5 In order to realize the NDR, the potential well is generally required to be uniform in thickness, i.e., the atomically flat interfaces are necessary. However, for nanometer-scale devices, the interfaces are no longer flat, particularly when the self-assembled nanostructures such as InAs dots on GaAs are used as the potential well. Although the interface roughness is known to cause a degradation of mobility for the in-plane transport in the quantum wells,^6,7 the roughness effect has not been studied sufficiently for the vertical tunneling transport through the DB structures.⁸

In this letter, the effect of the Si potential well roughness on the vertical tunneling transport through the Si/SiO₂ DB structure is studied. As a result, the increase of Si well roughness is found to cause a transition of tunneling mode from RT (flat limit) to single-electron tunneling (SET) (rough limit).

As shown in Fig. 1, three samples were prepared, which are referred to as samples A–C. Sample A has a Si/SiO₂ DB structure with relatively flat layers of Si well and SiO₂ barriers. Sample B also has a layered DB structure, but the top interface of Si well was intentionally roughened. For sample C, the Si well was further roughened, leading to the result that the Si well was separated into the Si dots. All the samples have single-crystalline Si as the potential well. In order to fabricate the single-crystalline Si well on the amorphous SiO₂, bonded silicon-on-insulator wafers with an ultrathin (2  nm) buried SiO₂ (BOX) layer were fabricated as the starting substrates (top left of Fig. 1).⁹ The ultrathin BOX works as the lower tunnel barrier in the DB structures. The top (001) Si layer was p-type (20    cm), while the (001) Si substrate was n⁺-type (<0.002    cm). Sample A was formed by the thinning of top Si (oxidation and oxide removal) and the subsequent oxidation for the upper SiO₂ barrier (2  nm). The Si well thickness was 2  nm. The atomic force microscope (AFM) image showed the rms roughness of 0.1  nm at the upper SiO₂ surface. For sample B, the fabrication process was similar to that for sample A, but before the oxidation for the upper SiO₂, the top Si surface was exposed to a buffered HF (BHF) solution (50%-HF:40%-NH₄F = 1:6, 30  s). In the BHF solution, the (001) Si layer was slowly etched anisotropically, leading to the formation of microscopic surface roughness.¹⁰ The AFM image showed an increased rms roughness of 0.3  nm. For sample C, in order to further increase the roughness, the surface corrugations shown at the top right of Fig. 1 were formed using a nanometer-scale local oxidation (LOCOS) process with the masks of naturally formed SiN islands.^11,12 Then, the upper SiO₂ (2  nm) was thermally grown. This oxidation divided the Si layer into the Si dots. As in the AFM image, the Si dots were formed with a diameter of ~20  nm, height of ~3  nm, and density of 1×10¹⁰  cm^–2. For the current–voltage (I–V) measurements at 15  K, Al top electrodes (50  µm×50  µm) were formed. Although the isolation between the diodes, such as the mesa patterning, was not performed, each of the diodes was electrically isolated from the other ones effectively, since the size of Al electrode is much larger than the vertical size of Si/SiO₂ DB structures. For sample C, about 10⁵ dots exist under the electrode.

Figure 1.

Figure 2(a) shows a typical I–V curve for sample A with the relatively flat Si well. As in our previous report,⁴ NDR is seen under the positive voltage applied to the Al top electrode (the electron tunneling from the n⁺-Si sbstrate). The current peak appears at 0.17  V, being in good agreement with 2E₀/e~0.18  V, where E₀ is the lowest resonance level (0.09  eV) derived from two of the six equivalent conduction bands (the tunneling electron mass of m_l = 0.92m₀). There is no NDR under the negative bias, because the off-resonance condition is absent for the tunneling from the Al electrode.⁴ Therefore, the overall feature is explained from the viewpoint of RT. However, the small peak current density (1.6×10^–6  A/cm²) and the large valley current (the peak-to-valley current ratio of 1.3) suggest that the electrons scattered during the tunneling are mixed.^13,14 In fact, the momentum relaxation time, estimated using a method in Ref. 15, was less than 0.1  ps (cf., for GaAs/AlGaAs,^13,15 typically the order of 0.1  ps). Taking account of the high scattering rate even for sample A with the relatively flat Si well, the scattering effect is anticipated to play a more important role for samples B and C having the increased well roughness. Actually, as described in the following, the results for these samples suggest that the increase of Si well roughness enhances the scattering, changing the mode of tunneling from RT.

Figure 2.

Figure 2(b) shows an example of I–V curve for sample B having the increased well roughness. Similar to sample A, NDR due to RT is seen, although the current peak appears at a larger voltage (~0.3  V) than that for sample A. This voltage increase is ascribed to the thinner Si well than that for sample A, which was caused by the BHF treatment. It is more important that, in addition to the NDR, inflections indicated by the arrows are seen below the NDR region. Actually, for the different electrodes on sample B, the inflections were commonly observed, while the small number of electrodes showed the NDR together with the inflections. Thus, the inflection is the most characteristic feature caused by the Si well roughness.

Such inflections were more clearly observed as the step-like current changes for sample C with the largest roughness among the samples. An example of the I–V curve is shown by the solid line in Fig. 2(c). A series of current steps appears, as indicated by the arrows. No NDR was observed below 0.2  V, around which the electrical breakdown occurred. The voltage spacing between the steps is almost constant to be 0.04  V, although the different electrodes on sample C showed the slightly different spacings (~0.1  V). The most possible reason to cause the step-like current change is the Coulomb staircase, i.e., SET, since the Si well was separated into the dots. In fact, as shown next by the simulation, the step-like change is explained from the viewpoint of SET.

Using a Monte Carlo simulation based on the orthodox SET theory, the I–V curve was simulated. The simulated curve is shown by the dashed line in Fig. 2(c). As in Fig. 3, an equivalent circuit composed of one Coulomb island (two tunnel junctions and an offset charge) was assumed. C₁ = C₂ = 3.7  aF was used with R₁ = 5  G  R₂ (= 5  M  ) and the offset charge of 0.25e. This leads to the charging energy e²/2(C₁ + C₂) of ~11  meV, which is much larger than the thermal energy k_BT of 1.3  meV at 15  K. The simulated curve is found to agree well with the experimental one, suggesting that the step-like current change occurs due to SET. Although there are lots of dots under the electrode, we believe that the current flows preferentially through one of the Si dots in such a low voltage range, as assumed in the equivalent circuit, otherwise such a periodic step-like change cannot be expected because of the dot-size distribution.¹⁶ Similar preferential current flow has been reported for the self-assembled InAs dots sandwiched by AlAs barriers,¹⁷ where the narrow current peak, similar to the RT peak for sample B, was observed and ascribed to RT through one of the InAs dots.

Figure 3.

In order to confirm the validity of interpretation for sample C that the step-like current change is derived from SET through one of the Si dots, the relationship was examined between the capacitance value of 3.7  aF in the simulation and the size of fabricated dot. Assuming simple plate capacitors as the SiO₂ barriers, the dot diameter is determined using the capacitance value by d = (i = 1 or 2), where _ox is the permittivity of SiO₂ (3.9₀) and t_ox is the thickness of SiO₂ barrier (2  nm). Substituting 3.7  aF to C_i, the diameter is obtained to be 17  nm. This value agrees well with the AFM observation in Fig. 1, supporting the notion that the SET current flows preferentially through one of the dots in the low voltage region. The preferential flow is probably derived from the slight difference of SiO₂ thickness among the dots, since the thickness difference on the atomic scale causes the change in the tunneling probability by more than one order of magnitude. It is likely that the fluctuation of SiO₂ thickness occurs when the randomly corrugated Si surface is oxidized, as in the case of sample C.

Similar to the case of sample C, the inflections observed for sample B are interpreted from the viewpoint of SET; the Coulomb islands are formed in the Si well, and the Coulomb staircase through one of the islands appears as the inflections. Although the Si layer is not separated into the dots, the Coulomb islands can be formed in the Si well due to the spatial fluctuation of quantized levels induced by the well roughness. For the Si well as thin as 2  nm, the thickness reduction by several atomic layers causes the increase of quantized energy as large as 0.1  eV, meaning that the thinner region works as the potential barrier to form the Coulomb islands. As for the lateral size of islands, in order to quantitatively explain the observed voltage spacing between the inflections (~0.1  eV), a tunnel capacitance as small as 1.6  aF, corresponding to the island diameter of 11  nm, is necessary. Although such a small island was difficult to see in the AFM image on the SiO₂ covered surface (bottom center of Fig. 1), the surface corrugations with the lateral size of ~10  nm can be observed on the bare Si surfaces after the BHF treatment. Therefore, it is concluded for sample B that, as the result of Coulomb island formation in the Si well by the roughness, the inflections appeared due to SET. Coexistence of the NDR due to RT and the SET-related inflections in Fig. 2(b) probably reflects that the portion, where RT governs the tunneling transport, remains partly under the macroscopic electrode. The narrow RT peak might reflect RT through the zero-dimensional state in one of the Si islands, being similar to the case for the InAs dots.¹⁷

From these results, the increase of Si well roughness was found to cause a transition of tunneling mode from RT to SET. For this transition, in addition to the Coulomb island formation, the scattering of electrons should be necessary to destroy the coherent RT, since SET is regarded to be a sequential tunneling. This suggests that the Si well roughness enhances the scattering during the tunneling. Such a roughness-enhanced scattering is probably related to the Heisenberg uncertainty principle, i.e., the increase of accuracy of electron position due to the island formation increases the uncertainty of electron momentum, leading to the relaxation of momentum conditions for the final states in the scattering events.

In summary, the increase of Si well roughness in the Si/SiO₂ DB structure was found to cause a transition of tunneling mode from RT to SET. This suggests that the Si well roughness induces (1) formation of the Coulomb islands in the Si well and (2) increase of the scattering events.

The authors would like to thank K. Osada and T. Mizuno for their support in the experiments. This work was partly supported by a Grant-in-Aid for Scientific Research from the Japan Society for the Promotion of Science.