STRESS-INDUCED PHENOMENA IN METALLIZATION: 8th International Workshop on Stress-Induced Phenomena in Metallization

8th International Workshop on Stress-Induced Phenomena in Metallization

Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing, Dresden, Germany ; Karen Maex, IMEC (Interuniversity MicroElectronics Center), Leuven, Belgium ; Paul S. Ho, The University of Texas at Austin, Interconnect and Packaging Group, Austin, TX, USA ; Hisao Kawasaki, Freescale Semiconductor, Austin, TX, USA ; Tomoji Nakamura, Fujitsu Laboratories, Ltd., Tokyo, Japan

Conference Location and Date: Dresden, Germany, 12-14 September 2005

Subseries: Materials Physics and Applications

Published February 2006; ISBN 0-7354-0310-4, One Volume, Print; 384 pages; 6 3/8 X 9 1/4 inches; Hardcover; $148.00

Readership: Scientists, engineers, and graduate students in research and development of microelectronic devices as well as technology integration, reliability and physical failure analysis - from universities and research institutes to semiconductor industry and equipment suppliers.

All papers were peer reviewed. This proceedings presents current research on issues related to stress-induced phenomena in on-chip metal interconnects and solder joints. Stresses arising in on-chip metal interconnects and surrounding dielectric materials due to thermal mismatch, electromigration, microstructure changes or process integration can lead to degradation and failure of microelectronic products. The implementation of low dielectric constant materials into the inlaid copper backend-of-line process has brought new challenges for process integration and reliability. Stress in solder joints can cause metallurgic effects like whisker growth, and subsequently failure. Understanding stress-related phenomena in new materials and structures is critical for development and integration of future metallic structures in microelectronic products.

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